The present invention relates to a semiconductor memory device, such as a dynamic random access memory having a capacitor of a three-dimensional structure suitable for high density device integration or to a static random access memory, and also to an embedded memory system LSI using those memory elements as cores.
For example, the dynamic random access memory (hereafter referred to as a dynamic RAM) has as an elemental memory unit a memory cell having connected thereto a capacitor to store electric charge as one bit of information and a switch transistor to write or read information into or from the capacitor. As it forms one memory cell by the small number of component elements as described above, the dynamic RAM is widely used in the main memory of computer equipment that requires a large capacity.
To increase the memory capacity of the dynamic RAM, it is necessary to miniaturize the memory cell area to increase the density of the memory cells.
However, in such a process, by the reduction of the memory cell area, the effective area of the charge-storage capacitor of the memory cell is decreased and the storage capacitance decreases. Therefore, the so-called soft-error phenomenon has manifested itself that information in the memory cell is reversed by a decrease of S/N ratio or by alpha-ray exposure, and has become a serious problem of reliability.
For this reason, there have been devised several memory cell structures that provide a large storage capacitance without increasing the area occupied by the memory cell. One of them is a memory cell having a stacked capacitor formed as a three-dimensional capacitor that uses the vertical material faces of the storage capacitance electrode as in the crown-shaped capacitor. Memory cells of this kind are described in JP-A-62-48062 and JP-A-62-128168, for example.
The memory cell of a 1-gigabit dynamic RAM is discussed in IEEE Int., Electron Devices Meeting, Technical Digest, pp.927-929 December (1994).
The dynamic RAM that the present inventors have conceived based on the memory cell structure disclosed in the above-mentioned literature is shown in FIG. 45. The structure and problem of this dynamic RAM will be described with reference to FIG. 45.
In FIG. 45, a transistor as a switch for the memory cell (hereafter a MISFET, which is in most general use, is used) includes a gate insulator 403, a gate electrode 404 and highly-doped n-type impurity regions 407, 408 as the source or the drain. In the highly-doped n-type impurity regions 407, 408, there are polycrystalline-silicon plugs 410 that pierce through a silicon dioxide film 409. There is an opening through a insulating film 412 on the polysilicon plug 410. Through this polysilicon plug, a data line (wiring electrode 413) formed on the insulating film 412 is electrically connected to the highly-doped n-type impurity region 407. In a space between the data line (wiring electrode 413) and a word lines (gate electrodes 404), there is formed a common opening, which runs through the insulating film 412 on the polysilicon plug 410 in the highly-doped n-type impurity region 408 and a silicon dioxide film 414 on the insulating film 412. Through this opening and the polysilicon plug 410, a storage electrode 415 of a crown-shaped capacitor formed of the above-mentioned polysilicon is electrically connected to the highly-doped n-type impurity region 408.
A capacitor dielectric film 416 is deposited on the storage electrode 415, and a plate electrode 417 is provided on the capacitor dielectric film 416. An aluminum wiring 419, formed on the silicon dioxide film 418 on the memory cell, is used as the cell selection wire or the main word line.
However, in a memory cell that has a capacitor above the data line as mentioned above, particularly, in the same memory cell when it is used for high device integration, the connection point of the data line (wiring electrode 413) and that of the capacitor electrode 415 are inevitably arranged very close to each other. Therefore, it becomes difficult to secure sufficient electrical insulation between the data line and the capacitor electrode due to mask misalignment during manufacture or a shift in dimensions (side etching) in dry etching in forming the opening of the insulating film 414. There is another problem. In matching of the data line to the opening of the insulating film 412, it becomes difficult to secure a sufficient allowance of the data line to overlie the opening. Owing to mask misalignment or a dimensional shift (side etching) in the dry etching of the wiring electrode 413 as the data line, there os a possibility that the polysilicon plug 410 is exposed from the above-mentioned opening and etched deeper.
Further, it has been necessary to arrange peripheral circuits, such as sense amplifiers, which are directly connected to the memory cell array, at the same pitch as the memory cells or at a twice larger pitch. In a memory for high device integration, which has a small area, it has been necessary to reduce the area occupied by the direct peripheral circuits, such as the sense amplifiers. Also in the indirect peripheral circuit, there are the same problems as with the memory cell as mentioned above in reducing the area occupied by the MISFET as a component part of the indirect peripheral circuit and in improving the wiring density.
Further, because a three-dimensional capacitor with a considerable height is used for the memory cell, if such a height difference between the memory cell portion and the indirect peripheral circuit portion is smoothed out, a problem has arisen that the depth of the contact holes in the indirect peripheral circuit portion increases and disconnection occurs in the indirect peripheral circuit.
To solve this problem, it is effective to use polysilicon plugs the same as used for the memory cells also for the contact areas of the indirect peripheral circuit. Doped polysilicon has conventionally been used to form polysilicon plugs, and therefore polysilicon plugs of doped polysilicon could be used for memory cells comprising transistors of one conductivity type.
However, in the indirect peripheral circuit where transistors of different conductivity types are generally used, polysilicon plugs of doped polysilicon of one conductivity type could not be used and therefore it has been difficult to reduce the areas of the indirect peripheral circuits.
On the other hand, as a plug material such as mentioned above, tungsten is well known which is deposited by chemical vapour deposition (CVD). In this case, tungsten can be used for the indirect peripheral circuit because tungsten serves as the diffusion barrier against impurities, but a problem has presented itself that tungsten has a low heat resistance and reacts with silicon during heat treatment at 600xc2x0 C. or higher.
Also in a static random access memory (hereafter referred to simply as a static RAM) cell made of transistors of opposite conductivity types formed on the principal surface of the silicon substrate, the memory cell area could be reduced by local interconnect technology. But, with technologies of this kind, it has not become possible to install the wiring layers of the indirect peripheral circuit.
Further, in an embedded memory system LSI (semiconductor integrated circuit system) using high-density dynamic, it is essential to use as many parts common to the memory cell and logic regions as possible.
An object of the present invention is to provide a semiconductor memory device, which includes a memory cell and indirect peripheral circuit and which has high component integration and high reliability.
Another object of the present invention is to provide a semiconductor memory device, which includes a memory cell and complementary transistors that form a sense amplifier or a logic circuit, and which has high component integration and high reliability.
Yet another object of the present invention is to provide a dynamic RAM having stacked capacitors in high density and with increased storage capacity.
A still further object of the present invention is to provide a dynamic RAM with a reduced memory cell area.
The present invention has been made to provide a semiconductor memory device which enables cost reduction by simplifying the manufacturing process.
According to the present invention, a semiconductor memory device having a memory cell and its indirect peripheral circuit, comprising:
transistors provided on a principal surface of a semiconductor surface;
a first insulating film provided on the transistors;
a plurality of first conductors (plug electrodes) passing through the first insulating film and being made of titanium nitride having superior covering properties; and
a first wiring provided on the principal surface of the first insulating film,
wherein the first wiring is connected to the transistors by the first conductors.
According to the present invention, in a memory cell region, a capacitor and a transistor formed on a principal surface of a second insulating film on the first insulating film are connected by the second conductor that pass through the first conductor and the second insulating film.
According to the present invention, the second conductor is formed so that its cylindrical portion is smaller than the diameter of the cylindrical portion of the first conductor.
Further according to the present invention, the first wiring is formed so that its line width is thinner than the diameter of the cylindrical portion of the first conductor.
Still further according to the present invention, a n-channel transistor and a p-channel transistor, which constitute a complementary transistor, are electrically connected by the first conductor.
According to the present invention, the first conductor made of titanium nitride effectively functions as the etching stopper to dry etching of the first wiring by using a suitable material for the first wiring and thus effectively utilizing a difference in etching rate between the first conductor and the first wiring.
Therefore, even if the first wiring connected to the first conductor is arranged in such a way that the first wiring does not completely cover the first conductor exposed at the principal surface of the first insulating film, the first conductor is prevented from being etched deeper when the first wiring is dry etched.
Because the diameter of the cylindrical portion of the second conductor and the line width of the first wiring are both thin, a contact does not occur between the second conductor and the first wiring.
Therefore, even if the area for the memory cell is reduced, a short-circuit never occurs between the capacitor and the data line, and because the capacitor is located above the data line, the required area for the capacitor in the memory cell can be increased to a maximum.
Further, because the titanium nitride serves as the barrier to diffusion of impurities, the first conductor is used to connect the n-channel transistor and the p-channel transistor in indirect peripheral circuit devices or in a static RAM cell formed by complementary transistors, so that the required areas for the indirect peripheral circuit and a memory cell can be reduced.